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FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR
ICS844071 Features
* * * * * * * *
One differential LVDS output Crystal oscillator interface, 18pF parallel resonant crystal (20.833MHz - 28.3MHz) Output frequency range: 62.5MHz - 170MHz VCO range: 500MHz - 680MHz RMS phase jitter at 150MHz, using a 25MHz crystal (900kHz - 7.5MHz): 0.45ps (typical) Full 3.3V or 2.5V operating supply 0C to 70C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
General Description
The ICS844071 is a Serial ATA (SATA)/Serial Attached SCSI (SAS) Clock Generator and a HiPerClockSTM member of the HiPerClocksTM family of high performance devices from IDT. The ICS844071 uses an 18pF parallel resonant crystal over the range of 20.833MHz - 28.3MHz. For SATA/SAS applications, a 25MHz crystal is used and either 75MHz or 150MHz may be selected with the FREQ_SEL pin. The ICS844071 has excellent <1ps phase jitter performance, over the 900kHz - 7.5MHz integration range. The ICS844071 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
ICS
Table 1. Common Configuration Table
Inputs Crystal Frequency (MHz) 25 25 26.041666 26.041666 26.5625 26.5625 FREQ_SEL 0 1 0 1 0 1 M 24 24 24 24 24 24 N 4 8 4 8 4 8 Multiplication Value M/N 6 3 6 3 6 3 Output Frequency (MHz) 150 75 156.25 78.125 159.375 79.675
Pin Assignment Block Diagram
FREQ_SEL
Pullup
VDD GND XTAL_OUT XTAL_IN
1 2 3 4
8 7 6 5
VDD Q nQ FREQ_SEL
XTAL_IN
OSC
XTAL_OUT
Phase Detector
VCO
500MHz - 680MHz
FREQ_SEL N 0 /4 1 (Default) /8
Q nQ
M = /24 (fixed)
ICS844071 8 Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
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Table 1. Pin Descriptions
Number 1 2 3, 4 5 6, 7 8 Name VDDA GND XTAL_OUT XTAL_IN FREQ_SEL nQ, Q VDD Power Power Input Input Output Power Pullup Type Description Analog supply pin. Power supply ground. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Frequency select pin. LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. Core supply pin.
NOTE: Pullup refers to intenal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN RPULLUP Parameter Input Capacitance Input Pullup Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characterisitcs is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, IO Continous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V 10mA 15mA 101.7C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = 3.3V 10%, TA = 0C to 70C
Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Power Supply Current Test Conditions Minimum 2.97 VDD - 0.12 Typical 3.3 3.3 Maximum 3.63 3.63 135 12 Units V V mA mA
Table 3B. Power Supply DC Characteristics, VDD = 2.5V 5%, TA = 0C to 70C
Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Power Supply Current Test Conditions Minimum 2.375 VDD - 0.12 Typical 2.5 2.5 Maximum 2.625 2.625 120 12 Units V V mA mA
Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 10% or 2.5V 5%, TA = 0C to 70C
Symbol VIH Parameter Input High Voltage Test Conditions VDD = 3.3V VDD = 2.5V Input Low Voltage Input High Current Input Low Current VDD = 3.3V VDD = 2.5V VDD = VIN = 3.63V or 2.625V VDD = 3.63V or 2.625V, VIN = 0V -150 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 5 Units V V V V A A
VIL IIH IIL
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Table 3D. LVDS DC Characteristics, VDD = 3.3V 10%, TA = 0C to 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.125 1.3 Test Conditions Minimum 275 Typical 365 Maximum 455 50 1.55 50 Units mV mV V mV
Table 3E. LVDS DC Characteristics, VDD = 2.5V 5%, TA = 0C to 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 0.89 1.2 Test Conditions Minimum 205 Typical 335 Maximum 465 50 1.48 50 Units mV mV V mV
Table 4. Crystal Characteristics
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 20.833 Test Conditions Minimum Typical Fundamental 28.3 50 7 1 MHz Maximum Units
pF mW
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AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = 3.3V 10%, TA = 0C to 70
Parameter Symbol fOUT Output Frequency RMS Phase Jitter, Random; NOTE 1 Output Rise/Fall Time Output Duty Cycle 150MHz, Integration Range: 900kHz - 7.5MHz 75MHz, Integration Range: 900kHz - 7.5MHz 20% to 80% 150 48 Test Conditions Minimum 62.5 0.45 0.46 400 52 Typical Maximum 170 Units MHz ps ps ps %
tjit(O)
tR / tF odc
NOTE 1: Please refer to Phase Noise Plots.
Table 5B. AC Characteristics, VDD = 2.5V 5%, TA = 0C to 70
Parameter Symbol fOUT Output Frequency RMS Phase Jitter, Random; NOTE 1 Output Rise/Fall Time Output Duty Cycle 150MHz, Integration Range: 900kHz - 7.5MHz 75MHz, Integration Range: 900kHz - 7.5MHz 20% to 80% 150 48 Test Conditions Minimum 62.5 0.56 0.60 400 52 Typical Maximum 170 Units MHz ps ps ps %
tjit(O)
tR / tF odc
NOTE 1: Please refer to Phase Noise Plots.
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Typical Phase Noise at 150MHz (3.3V)
0 -10 -20 -30 -40 -50 -60 -70 dBc Hz -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k Offset Frequency (Hz) 1M 10M 100M 150MHz RMS Phase Jitter (Random) 900kHz to 7.5MHz = 0.45ps (typical)
Noise Power
Raw Phase Noise Data
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Parameter Measurement Information
SCOPE
3.3V10% POWER SUPPLY + Float GND -
VDD VDDA
Qx
SCOPE
2.5V5% POWER SUPPLY + Float GND -
VDD VDDA
Qx
LVDS
nQx
LVDS
nQx
-
-
3.3V LVDS Output Load AC Test Circuit
2.5V LVDS Output Load AC Test Circuit
Phase Noise Plot
nQ
Noise Power
Q
t PW
Phase Noise Mask t
PERIOD
odc =
f1 Offset Frequency f2
t PW t PERIOD
x 100%
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS Phase Jitter
Output Duty Cycle/Pulse Width/Period
VDD out
80% Clock Outputs
80% VOD
DC Input
LVDS
out
20% tR tF
20%
VOS/ VOS
Output Rise/Fall Time
Offset Voltage Setup
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Parameter Measurement Information, continued
VDD

out
DC Input
LVDS
100
VOD/ VOD out
Differential Output Voltage Setup
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS44071 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VDDA pin.
3.3V or 2.5V VDD .01F VDDA .01F 10F 10
Figure 1. Power Supply Filtering
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Crystal Input Interface
The ICS844071 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_IN C1 33p X1 18pF Parallel Crystal XTAL_OUT C2 22p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
VDD
R1 Ro Rs 50 0.1f XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. General Disgram for LVCMOS Driver to XTAL Input Interface
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3.3V, 2.5V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V or 2.5V VDD 50
LVDS Driver R1 100
+
-
50
100 Differential Transmission Line
Figure 4. Tyical LVDS Driver Termination
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS844071. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS844071 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.63V * (135mA + 12mA) = 533.61mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.533W * 90.5C/W = 118.3C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection
JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 101.7C/W 1 90.5 2.5 89.8
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Reliability Information
Table 7. JA vs. Air Flow Table for a 8 Lead TSSOP
JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 101.7C/W 1 90.5 2.5 89.8
Transistor Count
The transistor count for ICS844071 is: 2533
Package Outline and Package Dimension
Package Outline - G Suffix for 8 Lead TSSOP Table 8. Package Dimensions
All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 8. Ordering Information
Part/Order Number ICS844071AG ICS844071AGT ICS844071AGLF ICS844071AGLFT Marking 4071A 4071A 071AL 071AL Package 8 Lead TSSOP 8 Lead TSSOP "Lead-Free" 8 Lead TSSOP "Lead-Free" 8 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev A Table T8 Page 9 13 Description of Change Added LVCMOS to XTAL Interface section. Ordering Information Table - added lead-free marking. Updated datasheet format. Date 9/26/07
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